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freescale semiconductor data sheet: technical data document number: mcf5275ec rev. 4, 02/2009 contents ? freescale semiconductor, inc., 2009. all rights reserved. the mcf5275 family is a highly integrated implementation of the coldfire ? family of reduced instruction set computing (r isc) microprocessors. this document describes pertinent features and functions characteristics of the mcf5275 family. the mcf5275 family includes the mcf5275, mcf5275l, mcf5274 and mcf5274l microprocessors. the differences between these parts are summarized in table 1 . this document is written from the perspective of the mcf5275 and unless otherwis e noted, the information applies also to the mcf5275l, mcf5274 and mcf5274l. the mcf5275 family deli vers a new level of performance and integrati on on the popular version 2 coldfire core with up to 159 (dhrystone 2.1) mips @ 166mhz. these highly integrated microprocessors build upon the widely used peripheral mix on the popular mcf5272 coldfire microprocessor (10/100 mbps ethernet mac and usb de vice) by adding a second 10/100 mbps ethernet ma c (mcf5274 and mcf5275) and hardware encrypti on (mcf5275l and mcf5275). 1 mcf5275 family configurations . . . . . . . . . . . . . . . . . . . 2 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 design recommendations . . . . . . . . . . . . . . . . . . . . . . . 9 6 mechanicals/pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18 9 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 mcf5275 integrated microprocessor family hardware specification by: microcontroller solutions group
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 mcf5275 family configurations freescale semiconductor 2 in addition, the mcf5275 fami ly features an enhanced multiply accumulate unit (ema c), large on-chip memory (64 kbytes sram, 16 kbytes configur able cache), and a 16-bit ddr sdram memory controller. these devices are ideal for cost-sensitive applicati ons requiring significant control processing for file management, connectivity, data buffering, and user interf ace, as well as signal processing in a variety of key markets such as security, imaging, networki ng, gaming, and medical. th is leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support. to locate any published errata or updates for this doc ument, refer to the coldfire products website at http://www.freesca le.com/coldfire . 1 mcf5275 family configurations table 1. mcf5275 family configurations module mcf5274l mcf5275l mcf5274 mcf5275 coldfire version 2 core with emac (enhanced multiply-accumulate unit) ???? system clock up to 166 mhz performance (dhrystone 2.1 mips) up to 159 instruction/data cache 16 kbytes (configurable) static ram (sram) 64 kbytes interrupt controllers (intc) 2222 edge port module (eport) ???? external interface module (eim) ???? 4-channel direct-memory access (dma) ???? ddr sdram controller ???? fast ethernet controller (fec) 1122 watchdog timer module (wdt) ???? 4-channel programmable interval timer module (pit) ???? 32-bit dma timers 4444 usb ???? qspi ???? uart(s) 3333 i 2 c ???? pwm 4444 general purpose i/o module (gpio) ???? cim = chip configuration module + reset controller module ???? debug bdm ???? jtag - ieee 1149.1 test access port ???? hardware encryption ? ? ? ? package 196 mapbga 256 mapbga
block diagram mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 3 2 block diagram the superset device in the mc f5275 family comes in a 256 mold array plastic ball grid array (mapbga) package. figure 1 shows a top-level block diagram of the mcf5275, the superset device. figure 1. mcf5275 block diagram 3features for a detailed feature list see the mcf5275 reference manual (mcf5275rm). 64 kbytes sram (8kx16)x4 eim v2 coldfire cpu intc0 watchdog pit0 jtag tap cache (1kx32)x4 pit1 pit2 pit3 4 ch dma uart 0 uart 1 i 2 c qspi dtim 0 dtim 1 dtim 2 dtim 3 timer pll clkgen uart 2 16 kbytes edge port sdramc chip ebi selects (to/from padi) (to/from ports cim (gpio) div emac dreq [1:0] intc1 arbiter (to/from sram backdoor) (to/from arbiter backdoor) skha rnga mdha cryptography modules dack [3:0] bdm (to/from intc) mux padi) jtag_en padi ? pin muxing bs [3:2] pwmx usb fec0 dtinx dtoutx rxdx txdx i2c_sda i2c_scl ddr qspi rtsx ctsx d[31:16] a[23:0] r/ w cs [3:0] ta tsiz [1:0] tea fec1 jtag_en trst tclk tms tdi tdo (to/from padi) (to/from padi) fast ethernet controller (fec1) fast ethernet controller (fec0) 4 ch pwm (to/from padi) usb 2.0 full speed (to/from padi)
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 signal descriptions freescale semiconductor 4 4 signal descriptions this section describes signals that connect off chip, including a tabl e of signal properties. for a more detailed discussion of the mcf5275 signals, consult the mcf5275 reference manual (mcf5275rm). table 2 lists the signals for the mcf5275 in functional group order. the ?dir ? column is the direction for the primary function of the pin. refer to section 6, ?mechanicals/pinouts ,? for package diagrams. note in this table and throughout this docum ent a single signal within a group is designated without square brackets (i.e., a24), while designations for multiple signals within a group use brackets (i.e., a[ 23:21]) and is meant to include all signals within the two br acketed numbers when these numbers are separated by a colon. note the primary functionality of a pin is no t necessarily its default functionality. pins that are muxed with gpio will default to their gpio functionality. table 2. mcf5274 and mcf5275 signal information and muxing signal name gpio alternate1 alternate2 dir. 1 mcf5274 mcf5275 256 mapbga mcf5274l mcf5275l 196 mapbga reset reset ? ?? in15 k12 rstout ? ?? on14 l12 clock extal ? ?? i l16 m14 xtal ? ?? om16 n14 clkout ? ?? ot12 p9 mode selection clkmod[1:0] ? ?? i n13, p13 m11, n11 rcon ? ?? ip8 m6 external memory interface and ports a[23:21] paddr[7:5] cs [6:4] ? o a11, b11, c11 a8, b8, c8 a[20:0] ? ? ? o a12, b12, c12, a13, b13, c13, a14, b14, c14, b15, c15, b16, c16, d14, d15, e14:16, f14:16 b9, d9, c9, c10, b10, a11, c11, b11, a12, d11, c12, b13, c13, d12, e11, d13, e12, f11, d14, e13, f13
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 5 d[31:16] ? ?? o m1, n1, n2, n3, p1, p2, r1, r2, p3, r3, t3, n4, p4, r4, t4, n5 j3, l1, k2, k3, m1, l2, l3, l4, k4, j4, m2, n1, n2, m3, m4, n3 bs [3:2] pbs [3:2] cas [3:2] ? o m3, r5 k1, l5 oe pbusctl[7] ? ? o k1 h4 ta pbusctl[6] ? ? i l13 k14 tea pbusctl[5] dreq1 ?i t8 ? r/w pbusctl[4] ? ? o p7 l6 tsiz1 pbusctl[3] dack1 ? o d16 b14 tsiz0 pbusctl[2] dack0 ? o g16 e14 ts pbusctl[1] dack2 ? o l4 h2 tip pbusctl[0] dreq0 ? o p6 ? chip selects cs [7:1] pcs[7:1] ? ? o d10:13, e13, f13, n7 d8, a9, a10, d10, b12, c14, p4 cs0 ? ? ? o r6 n5 ddr sdram controller ddr_clkout ? ?? ot7 p6 ddr_clkout ? ?? ot6 p5 sd_cs [1:0] psdram[7:6] cs [3:2] ? o m2, t5 h3, m5 sd_sras psdram[5] ? ? o l2 h1 sd_scas psdram[4] ? ? o l1 g3 sd_we psdram[3] ? ? o k2 g4 sd_a10 ???o n6 n4 sd_dqs [3:2] psdram[2:1] ??i/o m4, p5 j2, p3 sd_cke psdram[0] ? ? o l3 j1 sd_vref ? ? ? i a15, t2 a13, p2 external interrupts port irq [7:5] pirq[7:5] ?? i g13, h16, h15 f14, g13, g14 irq [4] pirq[4] dreq2 ? ih14 h11 irq [3:2] pirq[3:2] dreq [3:2] ? i j14, j13 h14, h12 table 2. mcf5274 and mcf5275 signal information and muxing (continued) signal name gpio alternate1 alternate2 dir. 1 mcf5274 mcf5275 256 mapbga mcf5274l mcf5275l 196 mapbga
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 signal descriptions freescale semiconductor 6 irq1 pirq[1] ?? i k13 j13 fec0 fec0_mdio pfeci2c[5] i2c_sda u2rxd i/o a7 a3 fec0_mdc pfeci2c[4] i2c_scl u2txd o b7 c5 fec0_txclk pfec0h[7] ?? i c3 c1 fec0_txen pfec0h[6] ?? o d4 c3 fec0_txd[0] pfec0h[5] ?? o g4 d2 fec0_col pfec0h[4] ?? i a6 b4 fec0_rxclk pfec0h[3] ?? i b6 b3 fec0_rxdv pfec0h[2] ?? i b5 c4 fec0_rxd[0] pfec0h[1] ?? i c6 d5 fec0_crs pfec0h[0] ?? i c7 a2 fec0_txd[3:1] pfec0l[7:5] ?? o e3, f3, f4 d1, e3, d3 fec0_txer pfec0l[4] ?? o d3 c2 fec0_rxd[3:1] pfec0l[3:1] ?? i d5, c5, d6 d4, b1, b2 fec0_rxer pfec0l[0] ?? i c4 e4 fec1 fec1_mdio pfeci2c[3] ?? i/o g1 ? fec1_mdc pfeci2c[2] ?? o g2 ? fec1_txclk pfec1h[7] ?? i c1 ? fec1_txen pfec1h[6] ?? o d2 ? fec1_txd[0] pfec1h[5] ?? o f1 ? fec1_col pfec1h[4] ?? i a5 ? fec1_rxclk pfec1h[3] ?? i b4 ? fec1_rxdv pfec1h[2] ?? i a3 ? fec1_rxd[0] pfec1h[1] ?? i b3 ? fec1_crs pfec1h[0] ?? i a4 ? fec1_txd[3:1] pfec1l[7:5] ?? o e1, e2, f2 ? fec1_txer pfec1l[4] ?? o d1 ? fec1_rxd[3:1] pfec1l[3:1] ?? i b1, b2, a2 ? fec1_rxer pfec1l[0] ?? i c2 ? table 2. mcf5274 and mcf5275 signal information and muxing (continued) signal name gpio alternate1 alternate2 dir. 1 mcf5274 mcf5275 256 mapbga mcf5274l mcf5275l 196 mapbga
signal descriptions mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 7 i 2 c i2c_sda pfeci2c[1] u2rxd ? i/o b10 b7 i2c_scl pfeci2c[0] u2txd ? i/o c10 a7 dma dack[3:0] and dreq [3:0] do not have a dedicated bond pads. please refer to the following pins for muxing: pcs3/pwm3 for dack3, pcs2/pwm2 for dack2, tsiz1 for dack1, tsiz0 for dack0, irq3 for dreq3 , irq2 and ta for dreq2 , tea for dreq1 , and tip for dreq0 . ? ? qspi qspi_cs[3:2] pqspi[6:5] pwm[3:2] dack[3:2] o r13, n12 p10, n9 qspi_cs1 pqspi[4] ? ? o t14 n10 qspi_cs0 pqspi[3] ? ? o p12 m9 qspi_clk pqspi[2] i2c_scl ? o t15 l11 qspi_din pqspi[1] i2c_sda ? i t13 m10 qspi_dout pqspi[0] ? ? o r12 l10 uarts u2rxd puarth[3] ? ? i t9 ? u2txd puarth[2] ? ? o r9 ? u2cts puarth[1] pwm1 ? i p9 ? u2rts puarth[0] pwm0 ? o r8 ? u1rxd puartl[7] ? ? i a9 a6 u1txd puartl[6] ? ? o b9 d7 u1cts puartl[5] ? ? i c9 c7 u1rts puartl[4] ? ? o d9 b6 u0rxd puartl[3] ? ? i a8 a4 u0txd puartl[2] ? ? o b8 a5 u0cts puartl[1] ? ? i c8 c6 u0rts puartl[0] ? ? o d7 b5 usb usb_speed pusbh[0] ? ? i/o g14 g11 usb_clk pusbl[7] ? ? i g15 f12 table 2. mcf5274 and mcf5275 signal information and muxing (continued) signal name gpio alternate1 alternate2 dir. 1 mcf5274 mcf5275 256 mapbga mcf5274l mcf5275l 196 mapbga
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 signal descriptions freescale semiconductor 8 usb_rn pusbl[6] ? ? i j16 h13 usb_rp pusbl[5] ? ? i j15 j11 usb_rxd pusbl[4] ? ? i l15 l14 usb_susp pusbl[3] ? ? o m13 n13 usb_tn pusbl[2] ? ? o k14 j14 usb_tp pusbl[1] ? ? o k15 j12 usb_txen pusbl[0] ? ? o l14 k13 timers (and pwms) dt3in ptimerh[3] dt3out u2rts i j4 g2 dt3out ptimerh[2] pwm3 u2cts o k3 g1 dt2in ptimerh[1] dt2out ? i j2 f3 dt2out ptimerh[0] pwm2 ? o j3 f4 dt1in ptimerl[3] dt1out ? i h1 f1 dt1out ptimerl[2] pwm1 ? o h2 f2 dt0in ptimerl[1] dt0out ? i h3 e1 dt0out ptimerl[0] pwm0 ? o g3 e2 bdm/jtag 2 dsclk ? trst ? i p14 p13 pstclk ? tclk ? o p16 p12 bkpt ? tms ? i r15 n12 dsi ? tdi ? i r16 m12 dso ? tdo ? o p15 k11 jtag_en ? ? ? i r14 p11 ddata[3:0] ? ? ? o p10, n10, p11, n11 m7, n7, p8, l9 pst[3:0] ? ? ? o t10, r10, t11, r11 p7, l8, m8, n8 test test ? ? ? i n9 n6 pll_test ? ? ? i m14 ? power supplies vddpll ? ? ? i m15 m13 table 2. mcf5274 and mcf5275 signal information and muxing (continued) signal name gpio alternate1 alternate2 dir. 1 mcf5274 mcf5275 256 mapbga mcf5274l mcf5275l 196 mapbga
design recommendations mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 9 5 design recommendations 5.1 layout ? use a 4-layer printed circuit board with the v dd and gnd pins connected directly to the power and ground planes for the mcf5275. ? see application note an1259 system design and layout techniques for noise reduction in mcu-based systems. ? match the pc layout trace width and routing to match trace length to operating frequency and board impedance. add termination (serie s or therein) to the traces to da mpen reflections. increase the pcb impedance (if possible) keeping the trace lengt hs balanced and short. then do cross-talk analysis to separate traces with significant parall elism or are otherwise "noisy". use 6 mils trace and separation. clocks get extra sepa ration and more precise balancing. 5.2 power supply ? 33uf, 0.1 f, and 0.01 f across each power supply vsspll ? ? ? i k16 l13 vss ? ? ? i a1, a10, a16, e5, e12, f6, f11, g7:10, h7:10, j1, j7:10, k7:10, l6, l11, m5, n16, r7, t1, t16 f7, f8, g6:9, h6:9, j7, j8 ovdd ? ? ? i e6:8, f5, f7, f8, g5, g6, h5, h6, j11, j12, k11, k12, l9, l10, l12, m9:11 e5:7, f5, f6, h10, j9, j10, k8:10 vdd ? ? ? i d8, h13, k4, n8 d6, g5, g12, l7 sd_vdd ? ? ? i e9:11, f9, f10, f12, g11, g12, h11, h12, j5, j6, k5, k6, l5, l7, l8, m6, m7, m8 e8:10, f9, f10, g10, h5, j5, j6, k5:7 1 refers to pin?s primary function. all pins which are configurable for gpio have a pullup enabled in gpio mode with the exception of pbusctl[7], pbusctl[4:0], paddr, pbs, psdram. 2 if jtag_en is asserted, these pins default to alte rnate 1 (jtag) functionality. the gpio module is not responsible for assigning these pins. table 2. mcf5274 and mcf5275 signal information and muxing (continued) signal name gpio alternate1 alternate2 dir. 1 mcf5274 mcf5275 256 mapbga mcf5274l mcf5275l 196 mapbga
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 design recommendations freescale semiconductor 10 5.2.1 supply voltage sequencing and separation cautions figure 2 shows situations in sequencing the i/o v dd (ov dd ), sdram v dd (sdv dd ), pll v dd (pllv dd ), and core v dd (v dd ). figure 2. supply voltage sequencing and separation cautions the relationship between sdv dd and ov dd is non-critical during power -up and power-down sequences. sdv dd (2.5v or 3.3v) and ov dd are specified relative to v dd . 5.2.1.1 power up sequence if ov dd /sdv dd are powered up with v dd at 0 v, then the sense circuits in the i/o pads cause all pad output drivers connected to the ov dd /sdv dd to be in a high impedance st ate. there is no limit on how long after ov dd /sdv dd powers up before v dd must powered up. v dd should not lead the ov dd , sdv dd, or pllv dd by more than 0.4 v during power ramp-up or high current will be in the internal esd protection diodes. the rise times on the power supplies should be slower than 1 s to avoid turning on the internal esd protection clamp diodes. the recommended power up sequence is as follows: 1. use 1 s or slower rise time for all supplies. 2. v dd /pllv dd and ov dd /sdv dd should track up to 0.9 v, then separate for the completion of ramps with ov dd /sd v dd going to the higher external voltages. one way to accomplish this is to use a low drop-out voltage regulator. sdv dd (2.5v) supplies stable 2 1 3.3v 2.5v 1.5v 0 time notes: vdd should not exceed ovdd, sdvdd or pllvdd by more than 0.4 v at any time, including power-up. recommended that vdd should track ovdd/sdvdd/pllvdd up to 0.9 v, then separate for completion of ramps. input voltage must not be greater than the supply voltage (ovdd, sdvdd, vdd, or pllvdd) by more than 0.5 v at any time, including during power-up. use 1 ms or slower rise time for all supplies. 1. 2. 3. 4. dc power supply voltage v dd , ov dd , sdv dd , pllv dd
design recommendations mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 11 5.2.1.2 power down sequence if v dd is powered down first, then sens e circuits in the i/o pads cause all output drivers to be in a high impedance state. there is no limit on how long after v dd powers down before ov dd , sdv dd , or pllv dd must power down. v dd should not lag ov dd , sdv dd , or pllv dd going low by more than 0.4 v during power down or undesired high current will be in the esd protection diodes. ther e are no requirements for the fall times of the power supplies. the recommended power down sequence is as follows: 1. drop v dd to 0 v. 2. drop ov dd /sdv dd /pllv dd supplies. 5.3 decoupling ? place the decoupling capacitors as cl ose to the pins as possible, but they can be outside the footprint of the package. ? 0.1 f and 0.01 f at each supply input 5.4 buffering ? use bus buffers on all data/address lines for al l off-board accesses and for all on-board accesses when excessive loading is expected. see electricals. 5.5 pull-up recommendations ? use external pull-up resistors on unused inputs. see pin table. 5.6 clocking recommendations ? use a multi-layer board wi th a separate ground plane. ? place the crystal and all other as sociated components as close to the extal and xtal (oscillator pins) as possible. ? do not run a high frequency trace around crystal circuit. ? ensure that the ground for the bypass capaci tors is connected to a solid ground trace. ? tie the ground trace to the ground pi n nearest extal and xtal. this prevents large loop currents in the vicinity of the crystal. ? tie the ground pin to the most solid ground in the system. ? do not connect the trace that connects the oscill ator and the ground plane to any other circuit element. this tends to ma ke the oscillator unstable. ? tie xtal to ground when an external oscillator is clocking the device.
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 design recommendations freescale semiconductor 12 5.7 interface recommendations 5.7.1 ddr sdram controller 5.7.1.1 sdram controller si gnals in synchronous mode table 3 shows the behavior of sdram signals in synchronous mode. 5.7.1.2 address multiplexing see the sdram controller module chapter in the mcf5275 reference manual for details on address multiplexing. 5.7.2 ethernet phy transceiver connection the fec supports an mii inte rface for 10/100 mbps ethern et and a seven-wi re serial interface for 10 mbps ethernet. the interface mode is selected by r_ cntrl[mii_mode]. in mi i mode, the 802.3 standard defines and the fec module supports 18 signals. these are shown in table 4 . table 3. synchronous dram signal connections signal description sd_sras synchronous row address strobe. indicates a valid sdram row address is present and can be latched by the sdram. sd_sras should be connected to the corresponding sdram sd_sras . do not confuse sd_sras with the dram controller?s sdram_cs[1:0] , which should not be interfaced to the sdram sd_sras signals. sd_scas synchronous column address strobe. indicates a valid column address is present and can be latched by the sdram. sd_scas should be connected to the corresponding signal labeled sd_scas on the sdram. sd_we dram read/write. asserted for write operations and negated for read operations. sd_cs [1:0] row address strobe. select each memory block of sdrams connected to the mcf5275. one sdram_cs signal selects one sdram block and connects to the corresponding cs signals. sd_cke synchronous dram clock enable. connected directly to the cke (clock enable) signal of sdrams. enables and disables the clock internal to sdram. when cke is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. sd_cke functionality is controlled by dcr[coc]. for designs using external multiplexing, setting coc allows sd_cke to provide command-bit functionality. bs [3:2] column address strobe. for synchronous operation, bs [3:2] function as byte enables to the sdrams. they connect to the dqm signals (or mask qualifiers) of the sdrams. ddr_clkout bus clock output. connects to the clk input of sdrams. table 4. mii mode signal description mcf5275 pin transmit clock fec n _txclk transmit enable fec n _txen transmit data fec n _txd[3:0] transmit error fec n _txer
design recommendations mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 13 the serial mode interface operates in what is generally referred to as amd mode. the mcf5275 configuration for seven-wire seri al mode connections to the exte rnal transceiver are shown in table 5 . refer to the m5275evb evaluation bo ard user?s manual for an example of how to connect an external phy. schematics for this board are accessi ble at the mcf5275 site by navigating to: http://www.freesca le.com/coldfire . 5.7.3 bdm use the bdm interface as shown in the m5275evb ev aluation board user?s manual. the schematics for this board are accessible at th e mcf5275 site by navigating to: http://www.freescale.com/coldfire . collision fec n _col carrier sense fec n _crs receive clock fec n _rxclk receive enable fec n _rxdv receive data fec n _rxd[3:0] receive error fec n _rxer management channel clock fec n _mdc management channel serial data fec n _mdio table 5. seven-wire mode configuration signal description mcf5275 pin transmit clock fec n _txclk transmit enable fec n _txen transmit data fec n _txd[0] collision fec n _col receive clock fec n _rxclk receive enable fec n _rxdv receive data fec n _rxd[0] unused, configure as pb14 fec n _rxer unused input, tie to ground fec n _crs unused, configure as pb[13:11] fec n _rxd[3:1] unused output, ignore fec n _txer unused, configure as pb[10:8] fec n _txd[3:1] unused, configure as pb15 fec n _mdc input after reset, connect to ground fec n _mdio table 4. mii mode (continued) signal description mcf5275 pin
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 mechanicals/pinouts freescale semiconductor 14 6 mechanicals/pinouts 6.1 256 mapbga pinout figure 3 is a consolidated mcf5274/75 pinout for the 256 mapbga package. table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages. figure 3. mcf5274 and mcf5275 pinout (256 mapbga) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a vss fec1_ rxd1 fec1_ rxdv fec1_ crs fec1_ col fec0_ col fec0_ mdio u0rxd u1rxd vss a23 a20 a17 a14 sd_ vref vss a b fec1_ rxd3 fec1_ rxd2 fec1_ rxd0 fec1_ rxclk fec0_ rxdv fec0_ rxclk fec0_ mdc u0txd u1txd i2c_ sda a22 a19 a16 a13 a11 a9 b c fec1_ txclk fec1_ rxer fec0_ txclk fec0_ rxer fec0_ rxd2 fec0_ rxd0 fec0_ crs u0cts u1cts i2c_ scl a21 a18 a15 a12 a10 a8 c d fec1_ txer fec1_ txen fec0_ txer fec0_ txen fec0_ rxd3 fec0_ rxd1 u0rts vdd u1rts cs7 cs6 cs5 cs4 a7 a6 tsiz1 d e fec1_ txd3 fec1_ txd2 fec0_ txd3 nc vss ovdd ovdd ovdd sd_vdd sd_vdd sd_vdd vss cs3 a5 a4 a3 e f fec1_ txd0 fec1_ txd1 fec0_ txd2 fec0_ txd1 ovdd vss ovdd ovdd sd_vdd sd_vdd vss sd_vdd cs2 a2 a1 a0 f g fec1_ mdio fec1_ mdc dt0out fec0_ txd0 ovdd ovdd vss vss vss vss sd_vdd sd_vdd irq7 usb_ speed usb_ clk tsiz0 g h dt1in dt1out dt0in nc ovdd ovdd vss vss vss vss sd_vdd sd_vdd vdd irq4 irq5 irq6 h j vss dt2in dt2out dt3in sd_vdd sd_vdd vss vss vss vss ovdd ovdd irq2 irq3 usb_rp usb_rn j k oe sd_we dt3out vdd sd_vdd sd_vdd vss vss vss vss ovdd ovdd irq1 usb_tn usb_tp vsspll k l sd_ scas sd_ sras sd_cke ts sd_vdd vss sd_vdd sd_vdd ovdd ovdd vss ovdd ta usb_ txen usb_ rxd extal l m d31 sd_cs1 bs3 sd_dqs3 vss sd_vdd sd_vdd sd_vdd ovdd ovdd ovdd nc usb_ susp pll_ test vddpll xtal m n d30 d29 d28 d20 d16 sd_a10 cs1 vdd test ddata2 ddata0 qspi_ cs2 clk mod1 rstout reset vss n p d27 d26 d23 d19 sd_dqs2 tip r/w rcon u2cts ddata3 ddata1 qspi_ cs0 clk mod0 trst / dsclk tdo/ dso tclk/ pstclk p r d25 d24 d22 d18 bs2 cs0 vss u2rts u2txd pst2 pst0 qspi_ dout qspi_ cs3 jtag_ en tms/ bkpt tdi/dsi r t vss sd_ vref d21 d17 sd_cs0 ddr_clk out ddr_clk out tea u2rxd pst3 pst1 clkout qspi_ din qspi_ cs1 qspi_ clk vss t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
mechanicals/pinouts mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 15 6.2 package dimensions - 256 mapbga figure 6 shows mcf5275 256 mapbga package dimensions. figure 4. 256 mapbga package dimensions x y d e laser mark for pin a1 identification in this area 0.20 metalized mark for pin a1 identification in this area m m 3 a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 10 11 12 13 14 15 16 e 15x e 15x b 256x m 0.25 y z m 0.10 x z s detail k view m-m rotated 90 clockwise s a z z a2 a1 4 0.15 z 0.30 256x 5 k notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.25 1.60 a1 0.27 0.47 a2 1.16 ref b 0.40 0.60 d 17.00 bsc e 17.00 bsc e 1.00 bsc s 0.50 bsc
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 mechanicals/pinouts freescale semiconductor 16 6.3 196 mapbga pinout figure 5 is a consolidated mcf5274l/75l pinout for the 196 mapbga package. table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages. figure 5. mcf5274l and mcf5275l pinout (196 mapbga) 1234567891011121314 a nc fec0_ crs fec0_ mdio u0rxd u0txd u1rxd i2c_scl a23 cs6 cs5 a15 a12 sd_ vref nc a b fec0_ rxd2 fec0_ rxd1 fec0_ rxclk fec0_ col u0rts u1rts i2c_sda a22 a20 a16 a13 cs3 a9 tsiz1 b c fec0_ txclk fec0_ txer fec0_ txen fec0_ rxdv fec0_ mdc u0cts u1cts a21 a18 a17 a14 a10 a8 cs2 c d fec0_ txd3 fec0_ txd0 fec0_ txd1 fec0_ rxd3 fec0_ rxd0 vdd u1txd cs7 a19 cs4 a11 a7 a5 a2 d e dt0in dt0out fec0_ txd2 fec0_ rxer ovdd ovdd ovdd sd_vdd2 sd_vdd2 sd_vdd2 a6 a4 a1 tsiz0 e f dt1in dt1out dt2in dt2out ovdd ovdd vss vss sd_vdd2 sd_vdd2 a3 usb_clk a0 irq7 f g dt3out dt3in sd_cas sd_we vdd vss vss vss vss sd_vdd2 usb_ speed vdd irq6 irq5 g h sd_sras ts sd_cs1 oe sd_vdd1 vss vss vss vss ovdd irq4 irq2 usb_rn irq3 h j sd_cke sd_dqs3 d31 d22 sd_vdd1 sd_vdd1 vss vss ovdd ovdd usb_rp usb_tp irq1 usb_tn j k bs3 d29 d28 d23 sd_vdd1 sd_vdd1 sd_vdd1 ovdd ovdd ovdd tdo/dso reset usb_ txen ta k l d30 d26 d25 d24 bs2 r/w vdd pst2 ddata0 qspi_ dout qspi_clk rstout vsspll usb_rxd l m d27 d21 d18 d17 sd_cs0 rcon ddata3 pst1 qspi_ cs0 qspi_din clkmod1 tdi/dsi vddpll extal m n d20 d19 d16 sd_a10 cs0 test ddata2 pst0 qspi_ cs2 qspi_ cs1 clkmod0 tms/bkpt usb_ susp xtal n p nc sd_ vref sd_dqs2 cs1 ddr_clk out ddr_clk out pst3 ddata1 clkout qspi_ cs3 jtag_en tclk/pst clk trst /dsc lk nc p 1234567891011121314
mechanicals/pinouts mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 17 6.4 package dimensions - 196 mapbga figure 6 shows mcf5275 196 mapbga package dimensions. figure 6. 196 mapbga package dimensions x tol laser mark for pin 1 identification in this area e 13x d e m s a1 a2 a 0.10 z 0.20 z z rotated 90 clockwise detail k 5 view m-m e 13x s m x 0.15 y z 0.08 z 3 b 196x metalized mark for pin 1 identification in this area 14 13 12 11 5 4 3 2 b c d e f g h j k l 4 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. y k m n p a 1 6 10 9 dim millimeters min max a 1.25 1.60 a1 0.27 0.47 a2 1.16 ref b 0.45 0.55 d 15.00 bsc e 15.00 bsc e 1.00 bsc s 0.50 bsc 196x
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 ordering information freescale semiconductor 18 7 ordering information 8 electrical characteristics this appendix contains electrical specification tables and refere nce timing diagrams for the mcf5275 microcontroller unit. this section contains deta iled information on power considerations, dc/ac electrical characteristi cs, and ac timing spec ifications of mcf5275. note the parameters specified in this appe ndix supersede any values found in the module specifications. 8.1 maximum ratings table 6. orderable part numbers freescale part number description package speed temperature mcf5274lvm166 mcf5274l risc microprocessor 196 mapbga 166 mhz 0 to +70 c MCF5274LCVM166 -40 to +85 c mcf5274vm166 mcf5274 risc microprocessor 256 mapbga 166 mhz 0 to +70 c mcf5274cvm166 -40 to +85 c mcf5275lcvm166 mcf5275l risc microprocessor 196 mapbga 166 mhz -40 to +85 c mcf5275cvm166 mcf5275 risc microprocessor 256 mapbga 166 mhz -40 to +85 c table 7. absolute maximum ratings 1, 2 1 functional operating conditions are given in dc el ectrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. rating symbol value unit core supply voltage v dd ? 0.5 to +2.0 v i/o pad supply voltage (3.3v) ov dd ? 0.3 to +4.0 v memory interface sstl 2.5v pad supply voltage sdv dd ? 0.3 to + 2.8 v memory interface sstl 3.3v pad supply voltage sdv dd ? 0.3 to +4.0 v pll supply voltage v ddpll ? 0.3 to +4.0 v digital input voltage 3 v in ? 0.3 to + 4.0 v extal pin voltage v extal 0 to 3.3 v xtal pin voltage v xtal 0 to 3.3 v instantaneous maximum current single pin limit (applies to all pins) 4, 5 i d 25 ma operating temperature range (packaged) t a (t l - t h ) ? 40 to 85 c storage temperature range t stg ? 65 to 150 c
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 19 8.2 thermal characteristics table 8 lists thermal resistance values 2 this device contains circuitry protecting against damag e due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circui t. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., v ss or o v dd ). 3 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 all functional non-supply pins are internally clamped to v ss and o v dd . 5 power supply must maintain regulation within operating o v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > o v dd ) is greater than i dd , the injection current may flow out of o v dd and could result in external power supply going out of regulation. ensure the external o v dd load shunts current greater than maximum injection current. this is the greatest risk when the mcu is not consumi ng power (ex; no clock).power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. table 8. thermal characteristics characteristic symbol 256mbga 196mbga unit junction to ambient, natural convection four layer board (2s2p) jma 26 1,2 1 jma and jt parameters are simulated in conformance with eia/j esd standard 51-2 for natural convection. freescale recommends the use of jma and power dissipation specific ations in the system design to prevent device junction temperatures from exceeding the rated s pecification. system designers should be aw are that device junction temperatures can be significantly influenced by board layout and surroundi ng devices. conformance to the device junction temperature specification can be verified by physical me asurement in the custom er?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. 32 1,2 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 23 1,2 29 1,2 c / w junction to board jb 15 3 3 thermal resistance between the die and the printed circ uit board in conformance with jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 20 3 c / w junction to case jc 10 4 4 thermal resistance between the die and the case top surf ace as measured by the cold plate method (mil spec-883 method 1012.1). 10 4 c / w junction to top of package natural convection jt 2 1,5 5 thermal characterization parameter indicating the tem perature difference between pa ckage top and the junction temperature per jedec jesd51-2. when gree k letters are not available, the thermal characterization parameter is written in conformance with psi-jt. 2 1,5 c / w maximum operating junction temperature t j 105 105 o c the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c jma = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o t j t a p d jma () + =
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 20 8.3 esd protection p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be ignored. an approximate relationship between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + jma p d 2 (3) where k is a constant pertaining to the particular part. k can be determi ned from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . table 9. esd protection characteristics 1, 2 1 all esd testing is in conformity with cdf-aec-q 100 stress test qualification for automotive grade integrated circuits. 2 a device is defined as a failure if after exposur e to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified other wise in the device specification. characteristics symbol value units esd target for human body model hbm 2000 v esd target for machine model mm 200 v hbm circuit description r series 1500 c 100 pf mm circuit description r series 0 c 200 pf number of pulses per pin (hbm) positive pulses negative pulses ? ? 1 1 ? number of pulses per pin (mm) positive pulses negative pulses ? ? 3 3 ? interval of pulses ? 1 sec p d kt j 273 c + () =
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 21 8.4 dc electrical specifications table 10. dc electrical specifications 1 characteristic symbol min max unit core supply voltage v dd 1.4 1.6 v i/o pad supply voltage ov dd 3.0 3.6 v pll supply voltage v ddpll 3.0 3.6 v sstl i/o pad supply voltage sdv dd 2.3 2.7 v sstl i/o pad supply voltage sdv dd 3.0 3.6 v sstl memory pads reference voltage (sd v dd = 2.5v) v ref 0.5 sd v dd ? 2 v sstl memory pads reference voltage (sd v dd = 3.3v) v ref 0.45 sd v dd ? 2 v input high voltage 3.3v i/o pads v ih 0.7 x ov dd ov dd + 0.3 v input low voltage 3.3v i/o pads v il v ss ? 0.3 0.35 x ov dd v output high voltage 3.3v i/o pads i oh = ?2.0 ma v oh ov dd - 0.5 ? v output low voltage 3.3v i/o pads i ol = 2.0ma v ol ?0.5v input hysteresis 3.3v i/o pads v hys 0.06 x v dd ?mv input high voltage sstl 3.3v/2.5v 3 v ih v ref + 0.3 sdv dd + 0.3 v input low voltage sstl 3.3v/2.5v 3 v il v ss - 0.3 v ref - 0.3 v output high voltage sstl 3.3v/2.5v 4 i oh = ?5.0 ma v oh sdv dd - 0.25v ? v output low voltage sstl 3.3v/2.5v 4 i ol = 5.0 ma v ol ?0.35v input leakage current v in = v dd or v ss , input-only pins i in -1.0 1.0 a high impedance (off-state) leakage current v in = v dd or v ss , all input/output and output pins i oz -1.0 1.0 a weak internal pull up device current, tested at v il max. 5 i apu -10 -130 a input capacitance 6 all input-only pins all input/output (three-state) pins c in ? ? 7 7 pf
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 22 load capacitance 7 low drive strength high drive strength c l ? ? 25 50 pf core operating supply current 8 master mode wait doze stop i dd ? ? ? ? 175 15 10 100 ma ma ma a i/o pad operating supply current master mode low power modes oi dd ? ? 250 250 ma a dc injection current 3, 9, 10, 11 v negclamp =v ss ? 0.3 v, v posclamp = v dd + 0.3 single pin limit total mcu limit, includes sum of all stressed pins i ic -1.0 -10 1.0 10 ma 1 refer to table 11 for additional pll specifications. 2 v ref is specified as a nominal value only instead of a range, so no maximum value is listed. 3 this specification is guaranteed by design and is not 100% tested. 4 the actual v oh and v ol values for sstl pads are dependent on the terminat ion and drive strength used. the specifications numbers assume no parallel termination. 5 refer to the mcf5274 signals chapter for pins having weak internal pull-up devices. 6 this parameter is characterized before qualification rather than 100% tested. 7 pf load ratings are based on dc loading and are provided as an indication of driver strength. high speed interfaces require transmission line analysis to determ ine proper drive strength and termination. 8 current measured at maximum system clock frequency, all modu les active, and default drive strength with matching load. 9 all functional non-supply pins are internally clamped to v ss and their respective v dd . 10 input must be current limited to the valu e specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative cl amp voltages, then use the larger of the two values. 11 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure the external v dd load shunts current greater than maximum injection current. this is the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. also, at power-up, system clock is not present during the power-up sequence until the pll has attained lock. table 10. dc electrical specifications 1 (continued) characteristic symbol min max unit
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 23 8.5 oscillator and phase lock loop (pllmrfm) electrical specifications table 11. pll electrical specifications 1 1 all values given are initial design targets and subject to change. characteristic symbol min max unit pll reference frequency range crystal reference external reference 1:1 mode (note: f sys/2 = 2 fref_1:1 ) f ref_crystal f ref_ext f ref_1:1 8 8 24 25 25 83 mhz core frequency clkout frequency 2 external reference on-chip pll frequency 2 all internal registers retain data at 0 hz. f core f sys/2 0 f ref / 32 166 83 83 mhz mhz mhz loss of reference frequency 3, 5 3 ?loss of reference frequency? is the reference frequency det ected internally, which transitions the pll into self clocked mode. f lor 100 1000 khz self clocked mode frequency 4, 5 f scm tbd tbd mhz crystal start-up time 5, 6 t cst ?10ms extal input high voltage crystal mode all other modes (dual controller (1:1), bypass, external) v ihext v ihext tbd tbd tbd tbd v extal input low voltage crystal mode all other modes (dual controller (1:1), bypass, external) v ilext v ilext tbd tbd tbd tbd v xtal output high voltage i oh = 1.0 ma v oh tbd ? v xtal output low voltage i ol = 1.0 ma v ol ?tbd v xtal load capacitance 7 530pf pll lock time 8 t lpll ? 750 s power-up to lock time 6, 9 with crystal reference without crystal reference 10 t lplk ? ? 11 750 ms s 1:1 mode clock skew (between clkout and extal) 11 t skew -1 1 ns duty cycle of reference 5 t dc 40 60 % f sys/2 frequency un-lock range f ul -3.8 4.1 % f sys/2 frequency lock range f lck -1.7 2.0 % f sys/2 clkout period jitter, 5, 6, 9,12, 13 measured at f sys/2 max peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over 2 ms interval) c jitter ? ? 5 .01 % f sys/2 frequency modulation range limit 14 , 15 (f sys/2 max must not be exceeded) c mod 0.8 2.2 % f sys/2 ico frequency. f ico = f ref * 2 * (mfd+2) 16 f ico 48 83 mhz
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 24 8.6 external interface timing characteristics table 12 lists processor bus input timings. note all processor bus timings are synchr onous; that is, input setup/hold and output delay with respect to the ri sing edge of a reference clock. the reference clock is the clkout output. all other timing relationships ca n be derived fro m these values. 4 self clocked mode frequency is the frequency that the pl l operates at when the reference frequency falls below f lor with default mfd/rfd settings. 5 this parameter is guaranteed by characterization before qualification rather than 100% tested. 6 proper pc board layout procedures must be followed to achieve specifications. 7 load capacitance determined from crystal manufacturer sp ecifications and includes circuit board parasitics. 8 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 9 assuming a reference is available at power up, lock time is measured from the time v dd and v ddpll are valid to rstout negating. if the crystal oscillator is being used as the reference for the pll, then the crystal start up time must be added to the pll lock time to determine the total start-up time. 10 t lpll = (64 * 4 * 5 + 5 x ) x t ref , where t ref = 1/f ref_crystal = 1/f ref_ext = 1/f ref_1:1 , and = 1.57x10 -6 x 2(mfd + 2) 11 pll is operating in 1:1 pll mode. 12 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f sys/2 . measurements are made with the device powered by filt ered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the jitter percentage for a given interval. 13 based on slow system clock of 33mhz maximum frequency. 14 modulation percentage applies over an interval of 10 s, or equivalently the modulation rate is 100khz. 15 modulation rate selected must not result in f sys/2 value greater than the f sys/2 maximum specified value. modulation range determined by hardware design. 16 f sys/2 = f ico / (2 * 2 rfd ) table 12. processor bus input timing specifications name characteristic 1 1 timing specifications have been indicated taking into account the full drive strength for the pads. symbol min max unit b0 clkout t cyc 12 ? ns control inputs b1a control input valid to clkout high 2 2 tea and ta pins are being referred to as control inputs. t cvch 9?ns b1b bkpt valid to clkout high 3 3 refer to figure a-19. t bkvch 9?ns b2a clkout high to control inputs invalid 2 t chcii 0?ns b2b clkout high to asynchronous control input bkpt invalid 3 t bknch 0?ns data inputs b4 data input (d[31:16]) valid to clkout high t divch 4?ns b5 clkout high to data input (d[31:16]) invalid t chdii 0?ns
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 25 timings listed in table 12 are shown in figure 7 . figure 7. general input timing requirements 8.7 processor bus output timing specifications table 13 lists processor bus output timings. table 13. external bus output timing specifications name characteristic symbol min max unit control outputs b6a clkout high to chip selects (cs [7:0]) valid 1 t chcv ?0.5t cyc + 5.5 ns b6b clkout high to byte enables (bs [3:2]) valid 1 t chbv ?0.5t cyc + 5.5 ns b6c clkout high to output enable (oe ) valid 1 t chov ?0.5t cyc + 5.5 ns b7 clkout high to control output (bs [3:2], oe ) invalid t chcoi 0.5t cyc + 1.0 ? ns b7a clkout high to chip selects invalid t chci 0.5t cyc + 1.0 ? ns address and attribute outputs b8 clkout high to address (a[23:0]) and control (ts , tsiz[1:0], tip , r/w) valid t chav ?9ns b9 clkout high to address (a[23:0]) and control (ts , tsiz[1:0], tip , r/w) invalid t chai 1.0 ? ns invalid invalid clkout (83mhz) t setup t hold input setup and hold t rise v h = v ih v l = v il valid t fall v h = v ih v l = v il input rise time input fall time * the timings are also valid for inputs sampled on the negative clock edge. inputs clkout b4 b5
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 26 read/write bus timings listed in table 13 are shown in figure 8 , figure 9 , and figure 10 . figure 8. read/write (internally terminated) sram bus timing data outputs b11 clkout high to data output (d[31:16]) valid t chdov ?9ns b12 clkout high to data output (d[31:16]) invalid t chdoi 1.0 ? ns b13 clkout high to data out put (d[31:16]) high impedance t chdoz ?9ns 1 cs , bs , and oe transition after the falling edge of clkout. table 13. external bus output timing specifications (continued) name characteristic symbol min max unit clkout csn a[23:0] r/w bs [3:2] d[31:16] ta (h) (h) s0 s2 s3 s1 s4 s5 s0 s1 s2 s3 s4 s5 tea (h) b6a b8 b7a b6c b7 b6b b7 b4 b5 b11 b12 b9 b9 b8 b6b b13 oe b0 b7 b9 ts tip b8 b8 b9 b8 b9 tsiz[1:0] b7a b6a b8
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 27 figure 9 shows a bus cycle terminated by ta showing timings listed in table 13 . figure 9. sram read bus cycle terminated by ta clkout csn a[23:0] oe r/w bs [3:2] ta (h) s0 s2 s3 s1 s4 s5 s0 s1 tea (h) b6a b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:16] b4 b5 b8 b9 ts b9 tip b8 tsiz[1:0]
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 28 figure 10 shows an sram bus cycle terminated by tea showing timings listed in table 13 . figure 10. sram read bus cycle terminated by tea clkout csn a[23:0] oe r/w bs [3:2] tea (h) s0 s2 s3 s1 s4 s5 s0 s1 ta (h) b6a b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:16] b8 b9 ts b9 tip b8 tsiz[ 1:0]
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 29 8.8 ddr sdram ac timing characteristics the ddr sdram controller uses sstl2 and i/o drivers. class i or cla ss ii drive strength is available and is user programmable. ddr clock timing specif ications are given in table 14 and figure 11 . figure 11. ddr clock timing diagram when using the ddr sdram cont roller the timing numbers in table 15 must be followed to properly latch or drive data onto the memory bus. all timi ng numbers are relative to the two dqs byte lanes. table 14. ddr clock timing specifications 1 1 sd v dd is nominally 2.5v. symbol characteristic min max unit v mp clock output mid-point voltage 1.05 1.45 v v out clock output voltage level -0.3 sdv dd + 0.3 v v id clock output differential voltage (peak to peak swing) 0.7 sdv dd + 0.6 v v ix clock crossing point voltage 1.05 1.45 v table 15. ddr timing num characteristic 1 symbol min max unit frequency of operation 2 tbd 83 mhz dd1 clock period (ddr_clkout) t ck 12 tbd ns dd2 pulse width high 3 t ckh 0.45 0.55 t ck dd3 pulse width low 3 t ckl 0.45 0.55 t ck dd4 ddr_clkout high to ddr address, sd_cke, sd_cs[1:0], sd_scas, sd_sras, sd_we valid t cmv ? 0.5 x t ck + 1 ns dd5 ddr_clkout high to ddr address, sd_cke, sd_cs , sd_scas , sd_sras , sd_we invalid t cmh 2?ns dd6 write command to first sd_dqs latching transition t dqss ?1.25t ck dd7 sd_dqs high to data and dm valid (write) - setup 4,5 t qs 1.5 ? ns dd8 sd_dqs high to data and dm invalid (write) - hold 4 t qh 1?ns dd9 sd_dqs high to data valid (read) - setup 6 t is ?1ns dd10 sd_dqs high to data invalid (read) - hold 7 t ih 0.25 x t ck + 1 ? ns dd11 sd_dqs falling edge to clkout high - setup t dss 0.5 ? ns dd12 sd_dqs falling edge to clkout high - hold t dsh 0.5 ? ns sdclk sdclk v ix v mp v ix v id
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 30 figure 13 shows a ddr sdram write cycle. figure 12. ddr_clkout and ddr_clkout crossover timing dd13 dqs input read preamble width (t rpre )t rpre 0.9 1.1 t ck dd14 dqs input read postamble width (t rpst )t rpst 0.4 0.6 t ck dd15 dqs output write preamble width (t wpre )t wpre 0.25 ? t ck dd16 dqs output write postamble width (t wpst )t wpst 0.4 0.6 t ck 1 all timing specifications are based on taking in to account, a 25pf load on the sdram output pins. 2 ddr_clkout operates at half the frequency of the pllmrfm output and the coldfire core. 3 t ckh + t ckl must be less than or equal to t ck . 4 d[31:24] is relative to sd_dqs3 and d[23:16] is relative to sd_dqs2 . 5 the first data beat is valid before the first rising edge of sd_dqs and after the sd_dqs write preamble. the remaining data beats are valid for each subsequent sd_dqs edge 6 data input skew is derived from each sd_dqs clock edge. it begins with a sd_dqs transition and ends when the last data line becomes valid. this input skew must include ddr memory ou tput skew and system level board skew (due to routing or other factors). 7 data input hold is derived from each sd_dqs clock edge. it begins with a sd_dqs transition and ends when the first data line becomes invalid. table 15. ddr timing (continued) num characteristic 1 symbol min max unit ddr_clkout ddr_clkout v ix v mp v ix v id
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 31 figure 13. ddr write timing ddr_clkout sd_cs n ,sd_we , dm[3:2] d[31:16] a[13:0] sd_sras ,sd_scas cmd row dd1 dd5 dd4 col wd1 wd2 wd3 wd4 dd7 sd_dqs [3:2] dd8 dd8 dd7 ddr_clkout dd3 dd2 dd6
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 32 figure 14. ddr read timing 8.9 general purpose i/o timing gpio can be configured for certain pins of th e qspi, ddr control, timers, uarts, fec0, fec1, interrupts and usb interfaces. when in gpio mode the timing specifica tion for these pins is given in table 16 and figure 15 . table 16. gpio timing num characteristic symbol min max unit g1 clkout high to gpio output valid t chpov ?10ns g2 clkout high to gpio output invalid t chpoi 1.0 ? ns g3 gpio input valid to clkout high t pvch 9?ns g4 clkout high to gpio input invalid t chpi 1.5 ? ns clkout sd_csn ,sd_we , sd_dqs [3:2] d[31:16] a[13:0] sd_sras ,sd_scas cmd row dd1 dd5 dd4 wd1 wd2 wd3 wd4 sd_dqs [3:2] dd9 clkout dd3 dd2 d[31:16] wd1 wd2 wd3 wd4 dd10 cl=2 cl=2.5 col dqs read preamble dqs read postamble dqs read preamble dqs read postamble cl = 2.5 cl = 2
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 33 figure 15. gpio timing 8.10 reset and configuration override timing reset and configuration override timing table 17. reset and configuration override timing (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) 1 1 all ac timing is shown with respect to 50% ov dd levels unless otherwise noted. num characteristic symbol min max unit r1 reset input valid to clkout high t rvch 9?ns r2 clkout high to reset input invalid t chri 1.5 ? ns r3 reset input valid time 2 2 during low power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. t rivt 5?t cyc r4 clkout high to rstout valid t chrov ?10ns r5 rstout valid to config. overrides valid t rovcv 0?ns r6 configuration override setup time to rstout invalid t cos 20 ? t cyc r7 configuration override hold time after rstout invalid t coh 0?ns r8 rstout invalid to configuration override high impedance t roicz ? 1 x t cyc ns g1 clkout gpio outputs g2 g3 g4 gpio inputs r1 r2 clkout reset rstout r3 r4 r8 r7 r6 r5 configuration overrides 1 : r4 (rcon, override pins]) 1. refer to the coldfire integration module (cim) section for more information.
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 34 8.11 fast ethernet ac timing specifications mii signals use ttl signal levels compatib le with devices operating at 5.0 v or 3.3 v. 8.11.1 mii receive signal timing (fec n _rxd[3:0], fec n _rxdv, fec n _rxer, and fec n _rxclk) the receiver functions correctly up to a fec n _rxclk maximum frequency of 25 mhz +1%. the processor clock frequency must exceed twice the fec n _rxclk frequency. table 18 lists mii receive channel timings. figure 16 shows mii receive sign al timings listed in table 18 . figure 16. mii receive signal timing diagram 8.11.2 mii transmit signal timing (fec n _txd[3:0], fec n _txen, fec n _txer, fec n _txclk) table 19 lists mii transmit channel timings. the transmitter functions correctly up to a fec n _txclk maximum frequency of 25 mhz +1%. the processor clock frequency must exceed twice the fec n _txclk frequency. table 18. mii receive signal timing num characteristic min max unit m1 fec n _rxd[3:0], fec n _rxdv, fec n _rxer to fec n _rxclk setup 5? ns m2 fec n _rxclk to fec n _rxd[3:0], fec n _rxdv, fec n _rxer hold 5? ns m3 fec n _rxclk pulse width high 35% 65% fec n _rxclk period m4 fec n _rxclk pulse width low 35% 65% fec n _rxclk period m1 m2 fec n _rxclk (input) fec n _rxd[3:0] (inputs) fec n _rxdv fec n _rxer m3 m4
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 35 figure 17 shows mii transmit si gnal timings listed in table 19 . figure 17. mii transmit signal timing diagram 8.11.3 mii async inputs signal timing (fec n _crs and fec n _col) table 20 lists mii asynchronous inputs signal timing. figure 18 shows mii asynchronous i nput timings listed in table 20 . figure 18. mii async inputs timing diagram table 19. mii transmit channel timing num characteristic min max unit m5 fec n _txclk to fec n _txd[3:0], fec n _txen, fec n _txer invalid 5? ns m6 fec n _txclk to fec n _txd[3:0], fec n _txen, fec n _txer valid ?25 ns m7 fec n _txclk pulse width high 35% 65% fec n _txclk period m8 fec n _txclk pulse width low 35% 65% fec n _txclk period table 20. mii asynchronous input signal timing num characteristic min max unit m9 fec n _crs, fec n _col minimum pulse width 1.5 ? fec n _txclk period m6 fec n _txclk (input) fec n _txd[3:0] (outputs) fec n _txen fec n _txer m5 m7 m8 fec n _crs m9 fec n _col
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 36 8.11.4 mii serial management channel timing (fec n _mdio and fec n _mdc) table 21 lists mii serial management channel timings. the fec functio ns correctly with a maximum mdc frequency of 2.5 mhz. figure 19 shows mii serial management channel timings listed in table 21 . figure 19. mii serial management channel timing diagram table 21. mii serial management channel timing num characteristic min max unit m10 fec n _mdc falling edge to fec n _mdio output invalid (minimum propagation delay) 0? ns m11 fec n _mdc falling edge to fec n _mdio output valid (max prop delay) ? 25 ns m12 fec n _mdio (input) to fec n _mdc rising edge setup 10 ? ns m13 fec n _mdio (input) to fec n _mdc rising edge hold 0 ? ns m14 fec n _mdc pulse width high 40% 60% mdc period m15 fec n _mdc pulse width low 40% 60% mdc period m11 fec n _mdc (output) fec n _mdio (output) m12 m13 fec n _mdio (input) m10 m14 m15
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 37 8.11.5 usb interface ac timing specifications table 22 lists usb interface timings. figure 20 shows usb interface timings listed in table 22 . figure 20. usb signals timing diagram table 22. usb interface timing num characteristic min max units us1 usb_clk frequency of operation 48 48 mhz us2 usb_clk fall time (v ih = 2.4 v to v il = 0.5 v) ? 2 ns us3 usb_clk rise time (v il = 0.5 v to v ih = 2.4 v) ? 2 ns us4 usb_clk duty cycle (at 0.5 x o v dd )4555% data inputs us5 usb_rp, usb_rn, usb_rxd valid to usb_clk high 6 ? ns us6 usb_clk high to usb_rp, usb_rn, usb_rxd invalid 6 ? ns data outputs us7 usb_clk high to usb_tp, usb_tn, usb_susp valid ? 12 ns us8 usb_clk high to usb_tp, usb_tn, usb_susp invalid 3 ? ns us7 usb_clk usb outputs us8 us5 us6 usb inputs t rise v h = v ih v l = v il t fall v h = v ih v l = v il input rise time input fall time us1
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 38 8.12 i 2 c input/output timing specifications table 23 lists specifications for the i 2 c input timing parameters shown in figure 21 . table 24 lists specifications for the i 2 c output timing parameters shown in figure 21 . table 23. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 start condition hold time 2 x t cyc ?ns i2 clock low period 8 x t cyc ?ns i3 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 x t cyc ?ns i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 x t cyc ?ns i9 stop condition setup time 2 x t cyc ?ns table 24. i 2 c output timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 1 1 output numbers depend on the value programme d into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta bl e 2 4 . the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2c_scl low period. the actual position is affe cted by the prescale and division values programmed into the ifdr; ho wever, the numbers given in ta b l e 2 4 are minimum values. start condition hold time 6 x t cyc ?ns i2 1 clock low period 10 x t cyc ?ns i3 2 2 because i2c_scl and i2c_sda are open-collector-t ype outputs, which the processor can only actively drive low, the time i2c_scl or i2c_sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ??s i4 1 data hold time 7 x t cyc ?ns i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ?3ns i6 1 clock high time 10 x t cyc ?ns i7 1 data setup time 2 x t cyc ?ns i8 1 start condition setup time (for repeated start condition only) 20 x t cyc ?ns i9 1 stop condition setup time 10 x t cyc ?ns
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 39 figure 21 shows timing for the values in table 23 and table 24 . figure 21. i 2 c input/output timings 8.13 dma timers timing specifications 8.14 qspi electrical specifications table 25. timer module ac timing specifications name characteristic 1 1 all timing references to clkout are given to its rising edge. min max unit t1 t0in / t1in / t2in / t3in cycle time 3 x t cyc ?ns t2 t0in / t1in / t2in / t3in pulse width 1 x t cyc ?ns table 26. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[3:0] to qspi_clk 1 510 t cyc qs2 qspi_clk high to qspi_dout valid. ? 10 ns qs3 qspi_clk high to qspi_dout invalid (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns i2 i6 i1 i4 i7 i8 i9 i5 i3 scl sda
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 40 figure 22. qspi timing 8.15 jtag and boundary scan timing table 27. jtag and boundary scan timing num characteristics 1 1 jtag_en is expected to be a static signal. he nce, it is not associated with any timing. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/2 j2 tclk cycle period t jcyc 4 x t cyc ?ns j3 tclk clock pulse width t jcw 26 ? ns j4 tclk rise and fall times t jcrf 03ns j5 boundary scan input data setup time to tclk rise t bsdst 4?ns j6 boundary scan input data hold time after tclk rise t bsdht 26 ? ns j7 tclk low to boundary scan output data valid t bsdv 033ns j8 tclk low to boundary scan output high z t bsdz 033ns j9 tms, tdi input data se tup time to tclk rise t tapbst 4?ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 ? ns j11 tclk low to tdo data valid t tdodv 026ns j12 tclk low to tdo high z t tdodz 08ns j13 trst assert time t trstat 100 ? ns j14 trst setup time (negation) to tclk high t trstst 10 ? ns qspi_cs[3:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2
electrical characteristics mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 41 figure 23. test clock input timing figure 24. boundary scan (jtag) timing figure 25. test access port timing figure 26. trst timing tclk v il v ih j3 j3 j4 j4 j2 (input) input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j5 j6 j7 j8 j7 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst 14 13
mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 electrical characteristics freescale semiconductor 42 8.16 debug ac timing specifications table 28 lists specifications for the de bug ac timing parameters shown in figure 28 . figure 27 shows real-time trace timing for the values in table 28 . figure 27. real-time trace ac timing figure 28 shows bdm serial port ac timing for the values in table 28 . figure 28. bdm serial port ac timing table 28. debug ac timing specification num characteristic 166 mhz units min max d0 pstclk cycle time ? 0.5 t cyc d1 pst, ddata to pstclk setup 4 ? ns d2 clkout to pst, ddata hold 1.0 ? ns d3 dsi-to-dsclk setup 1 x t cyc ?ns d4 1 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of pstclk. dsclk-to-dso hold 4 x t cyc ?ns d5 dsclk cycle time 5 x t cyc ?ns d6 bkpt input data setup ti me to pstclk rise 4 ? ns d7 bkpt input data hold time to pstclk rise 1.5 ? ns d8 pstclk high to bkpt high z 0.0 10.0 ns pstclk pst[3:0] d2 d1 ddata[3:0] dsi dso current next pstclk past current dsclk d3 d4 d5
documentation mcf5275 integrated microprocessor fami ly hardware specification, rev. 4 freescale semiconductor 43 9 documentation documentation regarding the mcf5275 and their deve lopment support tools is available from a local freescale distributor, a fr eescale semiconductor sa les office, the freescale lite rature distribution center, or through the freescal e web address at http://www.freescale.com/coldfire . 10 revision history table 29 provides a revision history fo r this hardware specification. table 29. document revision history rev. no. substantive change(s) 0 initial release. 1 added figure 6 . 1.1 removed duplicate information in the module descripti on sections. the information is all in the signals description table. 1.2 removed overview, features, signal descriptions, modes of operation, and address multiplexing sections. this information can be found in the mcf5275 reference manual. removed list of documentation in section 9, ?documentation .? . an up-to-date list is always available on our web site. changed clkout -> pstclk in section 8.16, ?debug ac timing specifications .? ta bl e 1 0 : update v dd spec from 1.35-1.65 to 1.4-1.6. ta bl e 1 3 : timings b6a, b6b, b6c, b7, b7a, b9, b12 updated: b6a, b6b, b6c maximum changed from ?0.5t cyc + 5? to ?0.5t cyc +5.5? b7, b7a minimum changed from ?0.5t cyc + 1.5? to ?0.5t cyc +1.0? b9, b11 minimum changed from ?1.5? to ?1.0? 1.3 added section 5.2.1, ?supply voltage sequencing and separation cautions .? added thermal characteri stics for 196 mapbga in ta bl e 8 . updated package dimensions drawing, figure 6 . 2 removed second sentence from section 8.11.1, ?mii receive signal timing (fecn_rxd[3:0], fecn_rxdv, fecn_rxer, and fecn_rxclk) ,? and section 8.11.2, ?mii transmit signal timing (fecn_txd[3:0], fecn_txen, fecn_txer, fecn_txclk) ,? regarding no minimum frequency requirement for txclk. removed third and fourth paragraphs from section 8.11.2, ?mii transmit si gnal timing (fecn_txd[3:0], fecn_txen, fecn_txer, fecn_txclk) ,? as this feature is not supported on this device. 3 corrected ordering information, ta b l e 6 . figure 2 : moved pllv dd from 1.5v to 3.3v supply line and correct ed relevant text in sections below table. ta bl e 1 0 : corrected maximum ?input high voltage 3.3v i/o pads?, v ih specification. 4 ta bl e 1 0 , added pll supply voltage row
document number: mcf5275ec rev. 4 02/2009 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp .

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